The present invention concerns a technique for manufacturing a semiconductor device and, more specifically, it relates to a technique which is effective when applied to the manufacture of a semiconductor device having a FIN type transistor including a FIN-shape semiconductor portion.
For proceeding with the high integration degree of integrated circuits configuring semiconductor devices, refinement of transistors has been conducted. However, existent planar type transistors have confronted to physical limit, and development of a novel transistor structure other than that of the planar type has been necessary for the refinement of the transistors.
Newly developed transistor structures include, as an example, a FIN-shape transistor of a vertical structure. The FIN type transistor is generally formed over a bulk silicon wafer or an SOI (Silicon On Insulator) wafer. The FIN type transistor formed on the bulk silicon wafer has an advantage that it can be formed at a low cost. Further, the FIN type transistor formed on the SOI wafer is advantageous for high integration degree. Further, it is capable of suppressing the short channel effect. Such FIN type transistors of vertical structure are disclosed, for example, in JP-A-2005-294789 and JP-A-2007-35957.
In any of them, since the impurity concentration profile in the FIN-shape semiconductor portion dominates the transistor characteristic in the same manner as in the planar type transistor, it is important to optimize the profile of the impurity concentration. For example, a doping method of introducing impurities uniformly to the FIN-shape semiconductor portion is described, for example, in Y. Sasaki, K. Okashita, K. Nakamoto, T. Kitaoka, B. Mizuno, and M. Ogura, IEDM Tech. Dig., pp. 917 to 920 (2008) and Genshu Fuse, “Ion Implantation Apparatus”, Electronic Materials, December, 2009, separate volume, p. 67 to 73.